In this work a novel technique to design ultra-low voltage (ULV), ultra-low power (ULP), inverter-based OTAs is presented. The proposal consists in utilizing a replica bias control loop applied to a body-driven inverter stage, with the aim of accurately setting both the DC current and the static output voltage, thus also centering the voltage transfer characteristic of the inverter cell. The proposed custom body-driven inverter attains rail-to-rail input common mode range, even at supply voltages as low as 0.3 V, and exhibits very stable performance under process, supply voltage and temperature (PVT) variations. The body-driven inverter cell is then exploited to implement a ULV, ULP OTA with small silicon area footprint, whose supply voltage can be scaled down to 0.3V. An extensive simulation campaign in a 180 nm CMOS technology has shown state-of-the-art performance in terms of small signal figure of merits, attaining very good robustness with respect to PVT variations.