A Bin-by-Bin Calibration with Neural Network for FPGA-Based Tapped-Delay-Line Time-to-Digital Converter | IEEE Conference Publication | IEEE Xplore

A Bin-by-Bin Calibration with Neural Network for FPGA-Based Tapped-Delay-Line Time-to-Digital Converter


Abstract:

The method of implementing TDC with FPGA carry chain is widely used, but the delay time of each TDC bin is greatly affected by the changes of operating temperature. At pr...Show More

Abstract:

The method of implementing TDC with FPGA carry chain is widely used, but the delay time of each TDC bin is greatly affected by the changes of operating temperature. At present, the commonly used methods can’t well fit the changing trend of each delay bin in long delay line under the influence of complex temperature changes. In this paper, a neural network calibration module based on MLP is proposed, in which 128 delay time data of delay line and corresponding temperature data transmitted to the host computer are used as training samples to establish MLP. When working, the delay time of each TDC bin can be given independently by knowing current temperature condition. Through experiments, the compensation of network calibration module on temperature changes is verified, and the network can be transplanted to different types of FPGA chips and run under various temperature changes. The TDC have a precision of 34ps.
Date of Conference: 17-22 July 2022
Date Added to IEEE Xplore: 05 September 2022
ISBN Information:
Conference Location: Guiyang, China

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