This paper presents an open source HW/SW co-design experimental platform based on behavioral benchmarks mapped onto a programmable SoC using High-Level Synthesis. HW/SW co-design has become extremely relevant in today's VLSI design processes. Due to the unstoppable increase in transistor count of integrated circuits (ICs), most ICs are currently heterogenous SoCs containing micro-processors, memories, interfaces and dedicated hardware accelerators. This has lead FPGA vendors to introduce programmable/configurable SoCs (CSoC), e.g. Altera's Cyclone/Arria/Stratix SoCs and Xilinx's Zynq family. At the same time, newer design methodologies are required to increase the design productivity like HLS. The main problem is that there are no benchmarks that can be directly mapped onto these CSoC using HLS to conduct research in HW/SW co-design as well as to teach HW/SW co-design. A HW/SW co-design experimental framework is presented here to bridge this gap. A set of synthesizable SystemC designs have been created and ported onto a Cyclone V SoC FPGA. The designs have been created in such a way that they can be fully executed on the embedded processor or accelerated by mapping the most computationally intensive kernel onto the reconfigurable fabric. A software layer allows the creation of different HW/SW configurations by allowing tasks to be executed on the embedded processor or mapped as hardware accelerator on the reconfigurable logic. The complete environment is open source and available online. A running time and energy comparison between the benchmarks mapped onto a desktop PC processor in ANSI-C and SystemC, an embedded ARM processor and the ASM+FPGA version are presented showing that the accelerated benchmarks do only lead to speed-ups compared to the embedded processor's version when the system's communication part (sending and receiving data) is lower than 50% of the total runtime. We believe that this open source HW/SW design platform is a good starting point to enco...