Mission critical and reliable systems on FPGA require error mitigation and recovery techniques to protect them from the errors caused by high energy radiation also known as Single Event Upsets (SEU). Different solutions have been reported with different trade-off of area-overhead and fault latency. We propose a low area-overhead self-reparable procedure based on an internal error recovery mechanism, which is monitored by an external watchdog timer in the role of diagnostic hardcore. The proposed procedure has been verified by extensive fault emulation experiments.