State of the art FPGAs comprise various architectural features providing the performance and flexibility required to comply with growing real-time demands of today's industrial applications. Nevertheless, the requirements on engineering expertise in order to exploit these platform features significantly increased during the past few years, consequently raising product costs and the time-to-market as well. Especially the feature of dynamic partial reconfiguration, enabling time-division multiplexing of resources within the reconfigurable fabric, is barely adopted by industry yet. This paper introduces a lightweight co-processing framework, taking advantage of an embedded processor closely coupled with the programmable logic inside the FPGA. The basic idea of this concept is to implement the sequential control flow of applications in software, while reconfigurable hardware accelerators may be utilized on-demand, in order to increase the performance on computation-intensive tasks. A hardware abstraction layer hides complex architectural processes and provides software engineers with a set of routines, enabling run-time requests and the interfacing of co-processors from within the code. Implementation details and sequences of operations are given and discussed.