This paper reports a 77-GHz phase-locked loop (PLL) for automobile radar system in 90-nm CMOS technology. To enhance the operation frequency range of the voltage-controlled oscillator (VCO) in the PLL, reversely tunable LC source degeneration technique is adopted. To improve the frequency locking range of the divide-by-3 injection-locked frequency divider (ILFD) in the PLL, a parallel inductor is used to parallel resonate the parasitic capacitance of the cross-coupled transistors. In addition, a phase and frequency detector (PFD) with enhanced D flip flops is used to effectively reduce the dead zone. The PLL consumes only 49.6 mW and exhibits an operation range of 2.4 GHz and reference sidebands of less than -56 dBc. The chip area of the PLL is 0.656 mm² excluding the test pads.