An ESL timing & power estimation and simulation framework for heterogeneous socs | IEEE Conference Publication | IEEE Xplore

An ESL timing & power estimation and simulation framework for heterogeneous socs


Abstract:

Consideration of an embedded system's timing behaviour and power consumption at system-level is an ambitious task. Sophisticated tools and techniques exist for power and ...Show More

Abstract:

Consideration of an embedded system's timing behaviour and power consumption at system-level is an ambitious task. Sophisticated tools and techniques exist for power and timing estimations of individual components such as custom hard- and software as well as IP components. But prediction of the composed system behaviour can hardly be made without considering all system components. In this paper we present an ESL framework for timing and power aware rapid virtual system prototyping of heterogeneous SoCs consisting of software, custom hardware and 3rd party IP components. Our proposed flow combines system-level timing and power estimation techniques with platform-based rapid prototyping. Virtual executable proto-types are generated from a functional C/C++ description, which then allows to study different platforms, mapping alternatives, and power management strategies. We propose an efficient code annotation technique for timing and power, that enables fast host execution and collection of power traces, based on domain-specific workload scenarios.
Date of Conference: 14-17 July 2014
Date Added to IEEE Xplore: 08 September 2014
Electronic ISBN:978-1-4799-3770-7
Conference Location: Agios Konstantinos, Greece

References

References is not available for this document.