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Modeling a reconfigurable system for computing the FFT in place via rewriting-logic | IEEE Conference Publication | IEEE Xplore

Modeling a reconfigurable system for computing the FFT in place via rewriting-logic


Abstract:

The growing adoption of reconfigurable architectures opens new implementation alternatives and creates new design challenges. In the case of dynamically reconfigurable ar...Show More

Abstract:

The growing adoption of reconfigurable architectures opens new implementation alternatives and creates new design challenges. In the case of dynamically reconfigurable architectures, the choice of an efficient architecture and reconfiguration scheme for a given application is a complex task. Tools for exploration of design alternatives at higher abstraction levels are needed. This paper describes the modeling and simulation of a dynamically reconfigurable hardware implementation of the fast Fourier transform (FFT) using rewriting-logic. It is shown that rewriting-logic can be used as a framework for fast design space exploration, providing a quick evaluation of different reconfigurable solutions.
Date of Conference: 08-11 September 2003
Date Added to IEEE Xplore: 23 September 2003
Print ISBN:0-7695-2009-X
Conference Location: Sao Paulo, Brazil

References

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