SoC design will require asynchronous techniques as the large parameter variations across the chip impose challenges to control delays in clock networks and other global signals efficiently. Today's state-of-the-art SoCs contain an ever-growing number of IP cores, each of which is immersed in its independent clock domain. When the IP core population increases and the minimum transistor size shrinks, it is challenging to keep all the different clock domains synchronized across the die while maintaining the considerable data bandwidth between them. One of the most promising solutions to this interconnect issue is the Globally Asynchronous, Locally Synchronous approach. Our goal is to provide an interconnection architecture which supports asynchronous communication between IPs working on its frequency. Instead of designing a fully asynchronous Network-on-Chip (NoC), our idea is to improve an existing synchronous NoC to support end-to-end asynchronous communication.