Traditional FPGA placement flows perform a fixed set of core optimizations. Not only do these optimizations have high computational cost, their application may adversely affect solution quality due to subtle features and patterns hidden within a circuit's netlist. In this paper, we develop a machine-learning based placement advisor that can be incorporated into a conventional FPGA placement flow to automatically select the most effective optimizations for improving CPU runtime and solution quality. When deployed within a state-of-the-art placement flow, our results show that the proposed placement advisor achieves a 17.26% improvement in CPU runtime, and a 2.26% improvement in total wirelength.