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Poster: Design consideration of 60 GHz low power low-noise amplifier in 65 nm CMOS | IEEE Conference Publication | IEEE Xplore

Poster: Design consideration of 60 GHz low power low-noise amplifier in 65 nm CMOS


Abstract:

This paper presents a design of fully differential low-noise amplifier (LNA) used for 60 GHz low power wireless communication in 65 nm CMOS technology. The proposed LNA c...Show More

Abstract:

This paper presents a design of fully differential low-noise amplifier (LNA) used for 60 GHz low power wireless communication in 65 nm CMOS technology. The proposed LNA consists of an input stage employing capacitive cross-coupling technique and an gain stage using current-reuse techniques. The simulated amplifier achieves both input and output matching better than −15dB, a forward gain of 15 dB, a noise figure of 4.7 dB, an input IP3 of −14dBm and the power consumption is 5 mW. The author also proposed a simple design method based on "black box" approach, which can be used for low power LNA design.
Date of Conference: 22-22 November 2016
Date Added to IEEE Xplore: 29 December 2016
ISBN Information:
Conference Location: Mons, Belgium

References

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