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A 65-nm CMOS Low-Power Front-End for 3rd Generation DNA Sequencing | IEEE Conference Publication | IEEE Xplore

A 65-nm CMOS Low-Power Front-End for 3rd Generation DNA Sequencing


Abstract:

A continuous-time, 65-nm CMOS, front-end for processing DNA sequencing measurements from biological nanopore sensors is presented. The measured design has an input referr...Show More

Abstract:

A continuous-time, 65-nm CMOS, front-end for processing DNA sequencing measurements from biological nanopore sensors is presented. The measured design has an input referred noise floor of 8.5 fA/√Hz for 100 pA DC current while consuming 10X less power. The chip also consists of an integrated ADC.
Published in: 2019 IEEE SENSORS
Date of Conference: 27-30 October 2019
Date Added to IEEE Xplore: 14 January 2020
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Conference Location: Montreal, QC, Canada

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