Abstract:
This paper presents an automatic VHDL code generation method based on the OpenMP parallel programming specification. In order to synthesize C code for loops into hardware...Show MoreMetadata
Abstract:
This paper presents an automatic VHDL code generation method based on the OpenMP parallel programming specification. In order to synthesize C code for loops into hardware, we applied the directives of OpenMP, which specifies portable implementations of shared memory parallel programs. The proposed design flow using this method is described and its implementation details are provided. Experimental results show that the generated vhdl code from OpenMP is competitive with optimized code.
Published in: 2016 IEEE 14th International Conference on Software Engineering Research, Management and Applications (SERA)
Date of Conference: 08-10 June 2016
Date Added to IEEE Xplore: 21 July 2016
ISBN Information: