Abstract:
A saystolic VLSI architecture is developed for a Sequential Monte Carlo (SMC)-Based equalizer for frequency-selective MIMO channels. The architecture is designed to explo...Show MoreMetadata
Abstract:
A saystolic VLSI architecture is developed for a Sequential Monte Carlo (SMC)-Based equalizer for frequency-selective MIMO channels. The architecture is designed to exploit the parallelism intrinsic to the algorithm. The system consists of the VLSI architecture for the QR decomposition, mean calculator, and the SMC blocks, where efficient architectures are employed for each block. Due to the pipelined implementation of the algorithm, the proposed architecture can be mapped to a smaller number of processors along different projection directions, yielding hardware structures with different performance and capabilities. Moreover, fixed-point simulation results are presented.
Published in: 2008 IEEE Workshop on Signal Processing Systems
Date of Conference: 08-10 October 2008
Date Added to IEEE Xplore: 17 November 2008
ISBN Information: