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Low-power pre-decoding based viterbi decoder for tail-biting convolutional codes | IEEE Conference Publication | IEEE Xplore

Low-power pre-decoding based viterbi decoder for tail-biting convolutional codes


Abstract:

Low-power and high-throughput Viterbi decoder (VD) for tail-biting convolutional codes is presented in this paper. First, a low complexity radix-4 VD with enhanced decodi...Show More

Abstract:

Low-power and high-throughput Viterbi decoder (VD) for tail-biting convolutional codes is presented in this paper. First, a low complexity radix-4 VD with enhanced decoding features such as end-state forcing and best-state trace back is presented. Second, simple predecoding is proposed to decrease the runtime of VD, resulting in significant power saving. The design is implemented in 0:9V TI 45-nm CMOS process at 100MHz for Long Term Evolution (LTE) [1] as application. More than 90% power saving is achieved with predecoding at a throughput of 120 Mbps and 0:2 dB SNR loss for 10−5 frame error rate.
Date of Conference: 07-09 October 2009
Date Added to IEEE Xplore: 17 November 2009
CD:978-1-4244-4335-2

ISSN Information:

Conference Location: Tampere, Finland

References

References is not available for this document.