Partitioning and optimization of high level stream applications for multi clock domain architectures | IEEE Conference Publication | IEEE Xplore

Partitioning and optimization of high level stream applications for multi clock domain architectures


Abstract:

In this paper we propose a design methodology to partition dataflow applications on a multi clock domain architecture. This work shows how starting from a high level data...Show More

Abstract:

In this paper we propose a design methodology to partition dataflow applications on a multi clock domain architecture. This work shows how starting from a high level dataflow representation of a dynamic program it is possible to reduce the overall power consumption without impacting the performances. Two different approaches are illustrated, both based on the post-processing and analysis of the causation trace of a dataflow program. Methodology and experimental results are demonstrated in an at-size scenario using an MPEG-4 Simple Profile decoder.
Published in: SiPS 2013 Proceedings
Date of Conference: 16-18 October 2013
Date Added to IEEE Xplore: 02 December 2013
Electronic ISBN:978-1-4673-6238-2

ISSN Information:

Conference Location: Taipei, Taiwan

References

References is not available for this document.