Abstract:
This paper presents four different architectures for the hardware acceleration of axis-parallel, oblique and non-linear decision tree ensemble classifier systems. Hardwar...Show MoreMetadata
Abstract:
This paper presents four different architectures for the hardware acceleration of axis-parallel, oblique and non-linear decision tree ensemble classifier systems. Hardware architectures for the implementation of a number of ensemble combination rules are also presented. The proposed architectures are optimized for size, making them particularly interesting for embedded applications where the size of the system is critical constraint. Proposed architectures are suitable for the implementation using FPGA and ASIC technology. Experiment results obtained using 29 datasets from the standard UCI Machine Learning Repository database suggest that the FPGA implementations offer significant improvement in the classification time in comparison with the pure software implementations.
Date of Conference: 17-19 September 2015
Date Added to IEEE Xplore: 12 November 2015
ISBN Information: