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A transistor array chip for the statistical characterization of process variability, RTN and BTI/CHC aging | IEEE Conference Publication | IEEE Xplore

A transistor array chip for the statistical characterization of process variability, RTN and BTI/CHC aging


Abstract:

In this work, a CMOS transistor array is presented, which allows performing process variability, Random Telegraph Noise and BTI/CHC aging characterization in a single chi...Show More

Abstract:

In this work, a CMOS transistor array is presented, which allows performing process variability, Random Telegraph Noise and BTI/CHC aging characterization in a single chip. The array, called ENDURANCE, integrates 3136 MOS transistors, for single and massive electrical testing. This chip, together with a dedicated measurement set-up, allows programming any of these electrical tests, considerably reducing the total time needed for aging measurements by using a parallelization technique.
Date of Conference: 12-15 June 2017
Date Added to IEEE Xplore: 17 July 2017
ISBN Information:
Conference Location: Giardini Naxos, Italy

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