This work focuses in using experimental measurements to extract the aspect ratio (W/L) for Gate-Enclosed or Annular MOSFETs. All measurements and calculations are performed with an automated virtual instrumentation (VI) environment developed in LabView. The VI was capable of extracting threshold voltage and low field mobility, needed for W/L calculation. An extraction procedure for the body effect factor is also presented. For validation purposes, extracted parameters were compared with those provided by the foundry (MOSIS) using traditional rectangular transistors. The extracted W/L was validated by comparing to Giraldo's experimental method. The SPICE BSIM 3 model parameters provided by the foundry is then modified using the extracted parameters including the aspect ratio. With this modification better simulation results were obtained. They were compared to the experimental measurements for an annular MOSFET drain voltage vs drain current characteristic curves at different gate voltages, showing an improvement of 58% when compared to the original non modified SPICE model parameters.