Abstract:
Integrated Circuits (ICs) are now very complex systems with a huge number of components integrated in a single design. As a consequence, pre-Silicon (pre-Si) analog IC ve...Show MoreMetadata
Abstract:
Integrated Circuits (ICs) are now very complex systems with a huge number of components integrated in a single design. As a consequence, pre-Silicon (pre-Si) analog IC verification, whether module-level or system-level, is an extremely time-consuming task. Verification in all possible operating condition (OC) configurations is practically impossible, due to the high number of OCs and the huge size of the OC hyper-space. In this context, advanced sampling methods for the OC hyper-space are required to offer better coverage with a smaller number of simulations. In addition, machine learning (ML) surrogate models are proposed to be used instead of time-consuming circuit simulations. In this context, we propose and evaluate several advanced sampling methods for the OC hyper-space and show that they provide results similar to the classical verification approach using 3x less simulations. Moreover, we show that training a ML surrogate model on this data leads to a much more effective model, that can be subsequently used to identify the circuit’s actual worst cases.
Date of Conference: 12-15 June 2022
Date Added to IEEE Xplore: 11 July 2022
ISBN Information: