Turbo decoding schemes achieve performance close to Shannon's theoretical limit but at the cost of decoder complexity. Log map turbo decoders are both computationally and memory intensive. Traditionally sliding window (SW) algorithms are used to reduce the decoding delay and memory requirements. In this paper we present a novel hardware architecture where we show that better scheduling and placement of memories (at the cost of performing more calculations) results in a much improved design both in terms of area and power