Abstract:
This paper describes a design of 8-bit x 8-bit unsigned multiplier. High-throughput rate is achieved by a new architecture implementing our earlier multiplication techniq...Show MoreMetadata
Abstract:
This paper describes a design of 8-bit x 8-bit unsigned multiplier. High-throughput rate is achieved by a new architecture implementing our earlier multiplication technique [1] in conventional register pipelining at the bit level. The multiplier is designed in 0.18-μm CMOS process. HSPICE simulation results indicate that our multiplier operating rates up to 6 GHz under the supply voltage of 1.8V. The empirical results show that our multiplier consumes only 63% (approx.) of the power of Baugh-Wooley multiplier with 40% reduction in latency.
Published in: Proceedings 2005 IEEE International SOC Conference
Date of Conference: 25-28 September 2005
Date Added to IEEE Xplore: 12 December 2005
Print ISBN:0-7803-9264-7