Abstract:
As technology scales down to the nanometer domain, leakage currents begin to contribute significantly to the total power consumption of the chip. In addition, it becomes ...Show MoreMetadata
Abstract:
As technology scales down to the nanometer domain, leakage currents begin to contribute significantly to the total power consumption of the chip. In addition, it becomes increasingly difficuilt to control the transistor device parameters. This causes increased heat dissipation in the chip and the degradation in the frequency of operation, thus compromising the reliability of the chip. Hence, it becomes necessary to model the leakage currents and variabilities observed in minimum geometry transistors early in the design flow, to be able to design a low-power, dense and robust cache architecture. In this paper, we present CacheSim, a cache memory simulator that includes compact models for both intra-die process parameter variations and leakage currents in the conventional cache architecture, to give an accurate estimate of memory power at the system level, and the cache access time.
Published in: 2007 IEEE International SOC Conference
Date of Conference: 26-29 September 2007
Date Added to IEEE Xplore: 20 June 2008
ISBN Information: