Abstract:
A new decoding technique for triple error Reed-Muller codes is proposed. In the best of our knowledge this is the first time that Reed-Muller Codes (RMC) as on-chip tripl...Show MoreMetadata
Abstract:
A new decoding technique for triple error Reed-Muller codes is proposed. In the best of our knowledge this is the first time that Reed-Muller Codes (RMC) as on-chip triple error correcting scheme is reported. We’ve compared the area, delay and power overhead for incorporating RMC and widely used Hamming Codes into a register file. The RMC on-chip results in 4.4X MTTF improvement with fault rate λ=10−4 and 5X reliability improvement in 512MB memory with λ=10−5 upsets/bit per day sacrificing area power and delay.
Published in: 2007 IEEE International SOC Conference
Date of Conference: 26-29 September 2007
Date Added to IEEE Xplore: 20 June 2008
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