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A fast pull-in scheme of plls using a triple path nonlinear phase frequency detector | IEEE Conference Publication | IEEE Xplore

A fast pull-in scheme of plls using a triple path nonlinear phase frequency detector


Abstract:

A fast pull-in and locking PLL-based frequency synthesizer with a triple-path nonlinear phase frequency detector (TPNPFD) scheme is presented. The proposed scheme can red...Show More

Abstract:

A fast pull-in and locking PLL-based frequency synthesizer with a triple-path nonlinear phase frequency detector (TPNPFD) scheme is presented. The proposed scheme can reduce the pull-in time significantly and speed-up the lock-in process. Both the charge pump current and the loop filter capacitors are reduced to 1/k of the conventional ones regardless of the change of the crossover frequency. Moreover a resistor scalar scheme is also presented in this novel architecture.
Date of Conference: 26-29 September 2007
Date Added to IEEE Xplore: 20 June 2008
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Conference Location: Hsinchu, Taiwan

References

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