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High defect tolerant low cost memory chips | IEEE Conference Publication | IEEE Xplore

High defect tolerant low cost memory chips


Abstract:

Memories are among the most dense integrated circuits fabricated, and so, have the highest rate of defects. This paper proposes a scheme for selecting the right redundanc...Show More

Abstract:

Memories are among the most dense integrated circuits fabricated, and so, have the highest rate of defects. This paper proposes a scheme for selecting the right redundancy in memory designs driven by the fabrication cost and the yield. It also proposes a new memory architecture that fills the gap between the existing all-or-none extremes with memories. Experiments show that the new scheme reduces cost by up to 70%.
Date of Conference: 26-29 September 2007
Date Added to IEEE Xplore: 20 June 2008
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Conference Location: Hsinchu, Taiwan

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