Programmable CRC circuit architecture | IEEE Conference Publication | IEEE Xplore

Abstract:

This paper presents the design and implementation of a fully programmable Cyclic Redundancy Check (CRC) computation circuit for System on a Chip (SoC) network processing ...Show More

Abstract:

This paper presents the design and implementation of a fully programmable Cyclic Redundancy Check (CRC) computation circuit for System on a Chip (SoC) network processing applications. The presented architecture provides flexibly whilst maintaining gigabit throughput rates for frame/packet processing using standard cell technology.
Date of Conference: 26-29 September 2007
Date Added to IEEE Xplore: 20 June 2008
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Conference Location: Hsinchu, Taiwan

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