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Performance analysis of IEEE defined LDPC codes under various decoding algorithms and their implementation on a reconfigurable instruction cell architecture | IEEE Conference Publication | IEEE Xplore

Performance analysis of IEEE defined LDPC codes under various decoding algorithms and their implementation on a reconfigurable instruction cell architecture


Abstract:

This paper builds a real time Programmable LDPC Decoder for decoding codes specified in IEEE 802.16 standard and discusses their performance under various decoding algori...Show More

Abstract:

This paper builds a real time Programmable LDPC Decoder for decoding codes specified in IEEE 802.16 standard and discusses their performance under various decoding algorithms. Out of the decoding algorithms, the modified Min-Sum SPA is selected for implementation and optimization on a reconfigurable instruction cell architecture. Different general and architecture specific optimization techniques are applied to enhance the throughput. With the architecture, a throughput of 20 Mbps has been achieved.
Date of Conference: 26-29 September 2007
Date Added to IEEE Xplore: 20 June 2008
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Conference Location: Hsinchu, Taiwan

References

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