Abstract:
Transaction level modeling is gaining increasing popularity with the increasing design complexity of the system-on-a-chip. Transaction level models are frequently built f...Show MoreMetadata
Abstract:
Transaction level modeling is gaining increasing popularity with the increasing design complexity of the system-on-a-chip. Transaction level models are frequently built from existing register transfer level models, which usually cause cycle errors. Measurable indicators of cycle errors are necessary, and their definitions are important. This paper presents the challenges in cycle error computation and our proposed method, although its effectiveness has not been proved formally. The main contribution of our study is to report an industrial experience with cycle error computation.
Published in: 2007 IEEE International SOC Conference
Date of Conference: 26-29 September 2007
Date Added to IEEE Xplore: 20 June 2008
ISBN Information: