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Analysis and design of an efficient complementary energy path adiabatic logic for low-power system applications | IEEE Conference Publication | IEEE Xplore

Analysis and design of an efficient complementary energy path adiabatic logic for low-power system applications


Abstract:

A complementary energy path adiabatic logic (CEPAL) designed for ubiquitous large-scaled digital systems achieves higher noise immunity, higher driving ability, and reduc...Show More

Abstract:

A complementary energy path adiabatic logic (CEPAL) designed for ubiquitous large-scaled digital systems achieves higher noise immunity, higher driving ability, and reduced power density than the prior quasi-static structure. By applying CEPAL to the clocked storage elements (i.e. DFFs) with a diode-shared scheme, the overall efficiency is dramatically improved without increasing the design overhead compared with the quasi-static implementation. A test module consists of an 8-bit CEPAL shift register (SFR) has been laid out in a 0.18-μm CMOS process. Post-layout analytic results, including parasitic effect and exhibiting the benefits of various aspects in the proposed fashion, are given as proof of concept.
Date of Conference: 26-29 September 2007
Date Added to IEEE Xplore: 20 June 2008
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Conference Location: Hsin Chu, Taiwan

References

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