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Assertion based design error diagnosis for core-based SoCs | IEEE Conference Publication | IEEE Xplore

Assertion based design error diagnosis for core-based SoCs


Abstract:

In this paper, we propose an assertion based methodology for diagnosing design errors inside a core-based SoC. In order to detect errors inside a core we have a sea of as...Show More

Abstract:

In this paper, we propose an assertion based methodology for diagnosing design errors inside a core-based SoC. In order to detect errors inside a core we have a sea of assertions together with a Local Assertion Processor (LAP) to handle the outputs of these assertions and diagnose the error position. The outputs of assertions are routed toward this processor through a boundary scan chain mechanism. After detecting and diagnosing the error, each LAP sends a specific data called error data to a Global Assertion Processor (GAP) which receives error data from all cores and performs necessary actions. We applied the proposed method on a simple multiprocessor SoC and showed the experimental results.
Date of Conference: 26-29 September 2007
Date Added to IEEE Xplore: 20 June 2008
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Conference Location: Hsinchu, Taiwan

References

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