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ESD protection design for Giga-Hz high-speed I/O interfaces in a 130-nm CMOS process | IEEE Conference Publication | IEEE Xplore

ESD protection design for Giga-Hz high-speed I/O interfaces in a 130-nm CMOS process


Abstract:

The electrostatic discharge (ESD) protection design for high-speed input/output (I/O) interfaces in a 130-nm CMOS process is proposed in this paper. First, the ESD protec...Show More

Abstract:

The electrostatic discharge (ESD) protection design for high-speed input/output (I/O) interfaces in a 130-nm CMOS process is proposed in this paper. First, the ESD protection devices were designed and fabricated to evaluate their ESD robustness and the parasitic effects in giga-hertz frequency band. With the knowledge on the dependence of device dimensions on ESD robustness and the parasitic capacitance, the ESD protection circuit for high-speed I/O interfaces was designed with minimum degradation on high-speed circuit performance but satisfactory high ESD robustness.
Date of Conference: 26-29 September 2007
Date Added to IEEE Xplore: 20 June 2008
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Conference Location: Hsinchu, Taiwan

References

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