The semiconductor technology continue its advnacement in 3D-IC circuit. The concept of 3D-IC introduces additional dimension in latest designs by using stack structures with through-silicon via (TSV). 3D ICs replace long interconnect in 2D ICs with TSV cells. However, optimization in terms of 3DIC is still immature in many aspects. There still exist problems in placement of standard cells and TSV cells in terms of timing optimization. In this paper, we proposed a methodology on cell placement by applying min-cut partitioning in one layer after layer assignment and address alignment constraint simultaneously. We applied Simulated Annealing to optimize timing and wirelength reduction. In final stage, a greedy legalization procedure is implemented to remove operlaps between cells and TSV cells. Experimental results show that both the wirelengths and the delay of critical paths in 3DICs are much superior compare to 2D ICs.