An energy-efficient level converter with high thermal variation immunity for sub-threshold to super-threshold operation | IEEE Conference Publication | IEEE Xplore

An energy-efficient level converter with high thermal variation immunity for sub-threshold to super-threshold operation


Abstract:

A multiple supply voltage scheme is an emerging approach to reduce power dissipation. The scheme requires a level converter as a bridge for different voltage domains. Con...Show More

Abstract:

A multiple supply voltage scheme is an emerging approach to reduce power dissipation. The scheme requires a level converter as a bridge for different voltage domains. Conventional level converters fail to work in sub-threshold region due to the pull-down devices and the pull-up devices operate in sub-threshold and super-threshold region respectively. By employing diode-connected PMOS transistors, multiple-threshold-voltage CMOS (MTCMOS), and stack leakage reduction techniques, the proposed cross-coupled level converter achieves small propagation delay, low power consumption, and best power-delay-product (PDP) performance. Also, the reverse short channel effect is utilized to provide our level converter better process/thermal variation immunity. We also propose a dual edge-triggered explicit-pulsed level-converting flip flop (LCFF) concept combining a DCVSPG latch and our level converter. The proposed cross-coupled level converter is designed using TSMC 65nm bulk CMOS technology. It functions correctly across all process corners for a wide input voltage range, from 150mV to 1V. The level converter has a propagation delay of 52ns and a power dissipation of 21nW when the input voltage is 150mV.
Date of Conference: 12-14 September 2012
Date Added to IEEE Xplore: 31 December 2012
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Conference Location: Niagara Falls, NY, USA

References

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