We are presenting a hybrid verification framework to design, verify and implement SOC protocols. The framework is based on the creation of specifications in terms of extended state transition tables, creation of templates for different phases of the design cycle and integration of these components in a design flow. The resultant design flow presents a tight integration of the debug/verification loop across different design stages that in turn reduce the time to market of the chip. This framework was applied to the design process of multiple SOC chips' production and the results have shown measurable enhancements.