FPGAs with integrated hard processors delivering a combination of performance, power savings and flexibility are becoming leading products in the market. Use of this platform calls for efficient hardware-software partitioning, which is crucial to the overall performance and reliability of these platforms. In this paper, we present a run-time efficient hardware-software partitioning technique for FPGAs called `KnapSim'. It employs two well-known heuristics - 0-1 Knapsack and Simulated Annealing algorithms, and provides near-optimal solutions. Experimental results show that performance of the proposed method is significantly better than Simulated Annealing in terms of quality of results and run-time.