Loading [a11y]/accessibility-menu.js
Efficient implementation of the AES algorithm for security applications | IEEE Conference Publication | IEEE Xplore

Efficient implementation of the AES algorithm for security applications


Abstract:

Throughput, area and power optimized designs for the advanced encryption standard algorithm are proposed in this paper. The presented designs are suitable for the encrypt...Show More

Abstract:

Throughput, area and power optimized designs for the advanced encryption standard algorithm are proposed in this paper. The presented designs are suitable for the encrypt-only AES-128 algorithm. Both designs integrate pipelining and iterative architectures in one design. This is achieved through applying the concept of partial loop unrolling where iterations and multistage pipelining are used to optimize area, throughput and dynamic power consumption. The first design achieves a throughput of 34.08 Gbps, an operating frequency of 266.29 MHz with 521 slice registers. The second design achieves a throughput of 34.09 Gbps, 674 slice registers and a frequency of 266.33 MHz on a Xilinx 14.2 Virtex-5 XC5VLX50-3 FPGA device. Both designs consumes an approximate value of 455 mW of dynamic power using Vivado 2014.4 on Zynq-7000 XC7Z010clq225-3 FPGA device.
Date of Conference: 06-09 September 2016
Date Added to IEEE Xplore: 24 April 2017
ISBN Information:
Electronic ISSN: 2164-1706
Conference Location: Seattle, WA, USA

References

References is not available for this document.