A novel scheme, spatially-correlated Design Dependent Critical-Path Monitor (DDCPM), is proposed, which can provide valuable references in deriving application-specific, process- and temperature-aware DVFS for aggressive power saving during runtime. Such DDCPM utilizes its unique spatial correlation feature and real-time sampling techniques to precisely sense the unexpected behavior introduced by over-scaled voltage under the operating conditions with random and mutually dependent Process-Voltage-Temperature (PVT) variations in each individual chip. Our experimental results obtained in two IPs implemented in TSMC 28 nm process node respectively show average step-wise 7.80% and 8.19% power could be reduced at a smaller granular level of voltage scaling, which corresponding maximum power reductions, 55.6% and 57.5% in Typical Corner could be finally achieved.