Finite state machine (FSM) plays an important role in digital circuit design. Since it stores the system states and controls system functionality, security vulnerabilities of FSM have been exploited extensively. Among the potential attacks, fault inject attack (FIA) is one of the most severe and most challenging to defend against. Unlike existing countermeasures, we propose a novel structure for FSM state flip flop design that can mitigate any kind of timing based FIAs. Our key idea is to sample the flip flop input signals multiple times during one clock cycle, and then compare these values to determine the correct one. This can effectively defeat all the FIAs based on violating FSM state setup time constraint. In addition, such design will make the design more robust against jitters. In order to reduce the design overhead, we use the low-cost transmission gates to implement the proposed latch and flip flop. We use Hspice to simulate the error conditions with delayed input data and jitter and the results confirm that our design is error resilient. We also implement the FSM in AES with our proposed flip flops and compare the area overhead with existing FIA countermeasures. Results show that the two state-of-the-art approaches have 2X and 4X area overhead than ours.