Abstract:
The hardware security domain in the recent years has experienced a plethora of threats of which side-channel attacks (SCAs) has been one of the emerging threats. These SC...Show MoreMetadata
Abstract:
The hardware security domain in the recent years has experienced a plethora of threats of which side-channel attacks (SCAs) has been one of the emerging threats. These SCAs function by exploiting the side-channels which invariably leak important data during an application’s execution. The information leaked through side-channels are inherent characteristics of the system and is often unintentional. This information can be microarchitectural or physical information such as power consumption, thermal maps, timing of the operation, acoustics, and cache-trace. Intercepting secret information based on the study of power signature is a subdivision of SCAs where power consumption information serves as a covert channel leaking crucial information about the executed operations. Such physical SCAs are known to be a significant threat to cryptosystems such as AES (Advances Encryption Standard) and can reveal the encryption key efficiently. To overcome such concerns and protect the data integrity, we introduce Power Swapper in this work. The proposed Power Swapper thwarts the attack by randomly choosing one of the multiple modules that perform the intended activity, but have power consumption different than a standard implementation and can lead to similar power consumption as one of the other modules that perform a different operation. To achieve this, we introduce carefully crafted swapping of the standby modules that are responsible for the AES operation thus deluding the attacker without hurting the crypto operations. To minimize the overheads, we design reconfigurable computing elements that can perform a given operation, but with different power consumption depending on the configuration. This methodology has been validated for the AES power analysis attack and the key information observed by the attacker is seen to be completely futile, indicating the success of the proposed method.
Date of Conference: 14-17 September 2021
Date Added to IEEE Xplore: 24 March 2022
ISBN Information: