The Internet-of-Things has given rise to an over-whelming number of resource-constrained devices which must communicate securely with a core server. Due to the variability in processing power among these devices, one lightweight crypto-graphic (LWC) algorithm cannot be standardized. This creates a problem for fog and cloud architectures, where a central server, is subsequently required to support many ciphers. Compounding this problem, LWC ciphers tend to require large numbers of rounds to achieve high security levels, thus occupying the server for unacceptable lengths of time. To minimize LWC overhead, we propose a novel parallel mapping of LWC ciphers and ReCPE, a reconfigurable, lightweight processing element (PE) for use in hardware security modules (HSM) and array processors such as smartNICs. The proposed design was synthesized for both FPGA and ASIC implementations. We validate the ReCPE architecture by comparing it with a baseline array processor and custom field programmable gate array (FPGA) LWC accelerators that use dynamic reconfiguration. The ReCPE architecture is shown to accelerate cryptographic processing by 2× when compared to a baseline PE, with 30% and 60% increases in logic and registers, respectively. Furthermore, we achieve a 50× improvement in dynamic reconfiguration environments when compared to custom FPGA accelerators.