Because it offers several benefits over other public-key cryptosystems much effort are done to make Hyper Elliptic Curve Cryptosystems (HECC) more practical, such as RSA, it offers a comparable level of security with a smaller key size. For this reason, HECCs can be used in embedded environments where speed, energy, power, chip and memory area are constrained. However, HEC use a complex mathematical background, so it's difficult to be implemented on hardware. They can be defined over real numbers, complex numbers and any other field. So we need arithmetic operations (addition, subtraction, multiplication and division) which have much application in cryptography and coding theory. We have to note that the overall performance of HECC is mainly determined by the speed of arithmetic operations. The most algorithms that manipulate these operations use polynomial coefficients in base 2 and they are defined over finite fields. But, the problem is clearly viewed over real field and simple to be presented. Arithmetic operations are based on the complexity of a mathematical problem, and to have an optimized architecture we need to optimize arithmetic operations. In this paper we describe a high performance, area efficient implementation of arithmetic operations in HECC over real field and a new design methodology is presented. The proposed architectures operations are implemented in FPGA.