This paper describe a new design approach of PLL architecture based on Sample and Hold Phase Detector (SHPD PLL). This architecture is a simplification and amelioration of the Inverse Sine Phase Detector (ISPD) PLL [1] [4]. The main difference between the two architectures, that we removed the Inverse Sine function in ISPD model, and replace it by an automatic gain control, which gives PLL more adaptation, stability, wide frequency range and fast response ability. Compared to ISPD PLL, the proposed SHPD PLL is 14 times, faster, more stable and 1.7 times frequency range wider than the, ISPD PLL.