In this paper, a sub-10 ps resolution, high precision and low power consumption Time-to-Digital Converter (TDC) is presented. The proposed TDC is based on the gateable pseudo-delay ring oscillator (GRO) architecture able to reach high linearity and wide input range. The time conversion resolution is equal to half of one inverter's propagation delay, which is improved by the thermometer decoder. The fractional output-code is obtained through a normalization unit, able to quantify phase errors and free calibrate measurements for counter-assisted ADPLL applications. To demonstrate the proposed concept, a 15-bit TDC has been implemented in a standard 90-nm CMOS process with an active core size of 80 μm × 345 μm. Using a 1.0 V supply, the topology achieves a resolution of 9.4 ps, and an average power consumption of 6.6 mW. A root-mean-square integral nonlinearity (INL) and differential nonlinearity (DNL) of respectively ±0.6 LSB and ±0.48 LSB is obtained with a relatively simplified calibration.