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Structure and software model of a parallel-vertical multi-input adder for FPGA implementation | IEEE Conference Publication | IEEE Xplore

Structure and software model of a parallel-vertical multi-input adder for FPGA implementation


Abstract:

In this paper parallel-vertical approach to realization of group summation has been analyzed. Analytical expression for synthesis of a 7-input single-digit adder have bee...Show More

Abstract:

In this paper parallel-vertical approach to realization of group summation has been analyzed. Analytical expression for synthesis of a 7-input single-digit adder have been realized. The structure and the program model for it implementation have been developed.
Date of Conference: 06-10 September 2016
Date Added to IEEE Xplore: 13 October 2016
ISBN Information:
Conference Location: Lviv, Ukraine

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