Abstract:
A model to estimate the bandwidth and interference in an interleaved memory system in a multiprocessor system is described. The model allows queuing on busy modules, and ...Show MoreMetadata
Abstract:
A model to estimate the bandwidth and interference in an interleaved memory system in a multiprocessor system is described. The model allows queuing on busy modules, and the results obtained show that previous results are rather pessimistic.
Published in: IEEE Transactions on Computers ( Volume: C-21, Issue: 8, August 1972)