The progress of semiconductor technology has been a dominant factor on the use of cellular arrays in digital computer design. When a subsystem is implemented in the form of a cellular array, it is important that the subsystem can be tested at the array terminals for the presence of a faulty cell in the array. In this paper some sufficient conditions for the testability of two-dimensional sequential cellular arrays are derived. These can be either unilaterally interconnected or bilaterally interconnected arrays where each cell has some storage elements and logic circuits.