Novel 4D CORDIC algorithms and hardware architecture for multiplying quaternions are presented, aimed at constant-coefficient multipliers. In our solution, microrotations are multiplications by hypercomplex numbers with only one non-zero imaginary part. Such transformations can be described using sparse matrices and implemented using less hardware resources than the iteration of the known quaternion CORDIC algorithm. Chip area can be saved because sparse microrotations can be computed using a permutation network and two-operand adders, without four-operand additions, which are necessary in the known solution. The obtainable area savings depend on the implementation technology and the architectures of adders and bit shifters but can be as large as 45 and 25 percent for ASIC and FPGA circuits, respectively. The circuitry simplifications come at the cost of slowing down computations: our approach improves the area-delay product, and a single sparse iteration can be executed up to 15 percent faster than the conventional one, but more microrotations are usually necessary to achieve the required accuracy. On the other hand, a sparse 4D iteration can be identified with microrotations of two 2D CORDICs which work in parallel. This makes convergence analysis easier than in the previous 4D solution, as it is sufficient to consider only two dimensions.