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CEnT: An Efficient Architecture to Eliminate Intra-Array Write Disturbance in PCM | IEEE Journals & Magazine | IEEE Xplore

CEnT: An Efficient Architecture to Eliminate Intra-Array Write Disturbance in PCM


Abstract:

Phase Change Memory (PCM), with its better scaling potential compared to DRAM, is seen as a promising candidate to replace or complement DRAM. The heat generated from a R...Show More

Abstract:

Phase Change Memory (PCM), with its better scaling potential compared to DRAM, is seen as a promising candidate to replace or complement DRAM. The heat generated from a RESET programming pulse to a PCM cell can disturb the neighboring cells which are not being programmed. Write disturbance (WD) poses a critical reliability challenge in high-density PCM memory with scaling below 20nm process technology node. Increasing the intra-cell space can eliminate the WD, however, it reduces the storage density which counteracts the benefits of scalability in PCM. At architectural level, a verify and correct (VnC) technique can be used to address this problem. However, this leads to an increased number of write operations, thus degrading performance, energy efficiency and memory lifetime. Due to its dependence on the type of programming operation and the state of the neighboring cell, WD is a data-dependent problem. Exploiting this property, encoding techniques have been proposed to reduce the frequency of WD-vulnerable data patterns. These techniques, however, do not eliminate the WD in an array and ultimately rely on the VnC method to ensure reliable memory operation. This article introduces a novel architecture, based on encoding and multi-level programming characteristics of PCM, to eliminate the intra-array WD in PCM. By eliminating WD and hence the need for a VnC operation, the proposed architecture improves performance, energy efficiency and memory lifetime. Our evaluation of the proposed architecture shows an average reduction of 57 percent in the number of writes (to service one write request) over the existing state-of-the-art intra-array WD-mitigation technique. Depending on the PCM write bandwidth, the proposed architecture can reduce the write service time by up to 27 percent, on average, compared to the existing best-performing technique. This leads to an average improvement of 15 percent in IPC. Additionally, by eliminating the overhead of a verify operation, the...
Published in: IEEE Transactions on Computers ( Volume: 71, Issue: 5, 01 May 2022)
Page(s): 992 - 1007
Date of Publication: 26 March 2021

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