In this paper, we present a novel finite-impulse response (FIR) filter synthesis technique that allows for aggressive voltage scaling by exploiting the fact that all filter coefficients are not equally important to obtain a ldquoreasonably accuraterdquo filter response. Our technique implements a level-constrained common-subexpression-elimination algorithm, where we can constrain the number of adder levels (ALs) required to compute each of the coefficient outputs. By specifying a tighter constraint (in terms of the number of adders in the critical path) on the important coefficients, we ensure that the later computational steps compute only the less important coefficient outputs. In case of delay variations due to voltage scaling and/or process variations, only the less important outputs are affected, resulting in graceful degradation of filter quality. The proposed architecture, therefore, lends itself to aggressive voltage scaling for low-power dissipation even under process parameter variations. Under extreme process variation and supply voltage scaling (0.8 V), filters implemented in the predictive technology model (PTM) 70 nm technology show an average power savings of 25%-30% with minor degradation in filter response in terms of normalized passband/stopband ripple (0.02 at a scaled voltage of 0.8 V compared with 0.005 at a nominal supply).